SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 1267

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30 DDR SDR SDRAM Controller (DDRSDRC) ......................................... 425
31 DMA Controller (DMAC) ....................................................................... 473
32 USB High Speed Port (UHPHS) ........................................................... 531
33 USB High Speed Device Port (UDPHS) .............................................. 537
6
29.5
29.6
29.7
29.8
29.9
29.10
29.11
29.12
29.13
29.14
29.15
29.16
30.1
30.2
30.3
30.4
30.5
30.6
30.7
31.1
31.2
31.3
31.4
31.5
31.6
31.7
32.1
32.2
32.3
32.4
32.5
SAM9G35
Application Example ......................................................................................381
Product Dependencies ..................................................................................381
External Memory Mapping .............................................................................382
Connection to External Devices ....................................................................382
Standard Read and Write Protocols ..............................................................387
Automatic Wait States ...................................................................................395
Data Float Wait States ...................................................................................399
External Wait .................................................................................................403
Slow Clock Mode ...........................................................................................409
Asynchronous Page Mode ............................................................................412
Programmable IO Delays ..............................................................................415
Static Memory Controller (SMC) User Interface ............................................416
Description .....................................................................................................425
Embedded Characteristics ............................................................................425
DDRSDRC Module Diagram .........................................................................427
Initialization Sequence ...................................................................................428
Functional Description ...................................................................................433
Software Interface/SDRAM Organization, Address Mapping ........................451
DDR SDR SDRAM Controller (DDRSDRC) User Interface ...........................455
Description .....................................................................................................473
Embedded Characteristics ............................................................................473
Block Diagram ...............................................................................................476
Functional Description ...................................................................................477
DMAC Software Requirements .....................................................................504
Write Protection Registers .............................................................................505
DMA Controller (DMAC) User Interface ........................................................506
Description .....................................................................................................531
Embedded Characteristics ............................................................................531
Block Diagram ...............................................................................................532
Product Dependencies ..................................................................................533
Typical Connection ........................................................................................535
11053B–ATARM–22-Sep-11