SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 59
SAM7L128
Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L128
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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13.3.3
13.3.4
13.3.4.1
Figure 13-3. General Reset State
6257A–ATARM–20-Feb-08
power_on_reset
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
NRST
SLCK
MCK
Brownout Manager
Reset States
General Reset
Please note that the NRST output is in high impedance state when the chip is in OFF mode.
The Brownout manager is embedded within the Supply Controller, please refer to the Supply
Controller section for a detailed description.
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
A general reset occurs when a Power-on-reset is detected, an Asynchronous Master Reset
(NRSTB pin ) is requested, a Brownout or a Voltage regulation loss is detected by the Supply
controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset
occurs.
All the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset.
As the RSTC_MR is reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL
defaults at value 0x0.
Figure 13-3
shows how the General Reset affects the reset signals.
XXX
EXTERNAL RESET LENGTH
= 2 cycles
Processor Startup
= 2 cycles
AT91SAM7L128/64 Preliminary
0x0 = General Reset
Freq.
Any
XXX
59
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