SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 216

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

24.5.2
24.5.3
24.6
24.6.1
216
Divider and PLL Block
AT91SAM7L128/64 Preliminary
Main Clock Frequency Counter
External Clock CLKIN
PLL Filter
The device features a Main Clock frequency counter that provides the frequency of the Main
Clock.
The Main Clock frequency counter starts incrementing at the Main Clock speed after the next ris-
ing edge of the Slow Clock as soon as MAINCKON is set to 1.Then, at the 16th falling edge of
Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock Frequency Register
(CKGR_MCFR) is set and the counter stops counting. Its value can be read in the MAINF field of
CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so
that the frequency of the 2 MHz Fast RC Oscillator or CLKIN input signal can be determined.
The user can input a clock on the device. In this case, the user has to provide the external clock
signal on the CLKIN pin. The programmer has to be sure to set the MCKSEL bit in the Clock
Generator Main Oscillator Register (CKGR_MOR) to 1 for the external clock to operate properly.
The user can check the MAINSELS bit in the Power Management Status Register (PMC_SR) to
check that the selection has been completed.
Note that the user must be sure to put MCKSEL bit to 1 only when an external clock is applied
on CLKIN. The user does not need to check MAINRDY bit when switching to CLKIN.
Input characteristics of the CLKIN pin are given in the Electrical Characteristics section.
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. How-
ever, the user must respect the PLL minimum input frequency when programming the divider.
Figure 24-4
Figure 24-4. Divider and PLL Block Diagram
The PLL requires connection to an external second-order filter through the PLLRC pin.
24-5
shows a schematic of these filters.
shows the block diagram of the divider and PLL block.
SLCK
SLCK
Divider = 1
DIV
PLLCOUNT
Counter
PLLRC
PLL
MUL
PLL
OUT
LOCK
PLLCK
6257A–ATARM–20-Feb-08
Figure