SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 141

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19. Enhanced Embedded Flash Controller (EEFC)
19.1
19.2
19.2.1
19.2.2
19.3
19.3.1
6257A–ATARM–20-Feb-08
Overview
Product Dependencies
Functional Description
Power Management
Interrupt Sources
Embedded Flash Organization
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with
the 32-bit internal bus. Its 128-bit wide memory interface increases performance. It also man-
ages the programming, erasing, locking and unlocking sequences of the Flash using a full set of
commands. One of the commands returns the embedded Flash descriptor definition that informs
the system about the Flash organization, thus making the software generic.
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Man-
agement Controller has no effect on its behavior.
The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the Memory
Controller internal source of the Advanced Interrupt Controller. Using the Enhanced Embedded
Flash Controller (EEFC) interrupt requires the AIC to be programmed first. The EEFC interrupt is
generated only on FRDY bit rising. To know the Flash status, MC Flash Status Register should
be read each time a system interrupt (SYSIRQ, periph ID = 0) occurs.
The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is
composed of:
The embedded Flash size, the page size, the lock regions organization and GPNVM bits defini-
tion are described in the product definition section. The Enhanced Embedded Flash Controller
(EEFC) returns a descriptor of the Flash controlled after a get descriptor command issued by the
application (see
• One memory plane organized in several pages of the same size.
• Two 128-bit read buffers used for code read optimization.
• One 128-bit read buffer used for data read optimization.
• One write buffer that manages page programming. The write buffer size is equal to the page
• Several lock bits used to protect write/erase operation on several pages (lock region). A lock
• Several bits that may be set and cleared through the Enhanced Embedded Flash Controller
size. This buffer is write-only and accessible all along the 1 MByte address space, so that
each word can be written to its final address.
bit is associated with a lock region composed of several pages in the memory plane.
(EEFC) interface, called General Purpose Non Volatile Memory bits (GPNVM bits).
“Getting Embedded Flash Descriptor” on page
AT91SAM7L128/64 Preliminary
147).
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