SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 324
SAM7L128
Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L128
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Figure 29-6. Master Write with One Data Byte
Figure 29-7. Master Write with Multiple Data Byte
Figure 29-8. Master Write with One Byte Internal Address and Multiple Data Bytes
29.7.5
324
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
AT91SAM7L128/64 Preliminary
Master Receiver Mode
S
Write THR (Data n)
S
DADR
TXCOMP
DADR
TXRDY
TWD
When no more data is written into the TWI_THR, the master generates a stop condition to end
the transfer. The end of the complete transfer is marked by the TWI_TXCOMP bit set to one.
See
TXRDY is used as Transmit Ready for the PDC transmit channel.
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
W
Write THR (DATA)
S
Figure
W
A
29-6,
DADR
IADR(7:0)
A
Figure
Write THR (Data n+1)
DATA n
W
29-7, and
A
A
DATA n
Write THR (Data n+1)
A
Figure
DATA
29-8.
A
Write THR (Data n+x)
DATA n+5
Last data sent
(ACK received and TXRDY = 1)
A
STOP sent automaticaly
Write THR (Data n+x)
DATA n+5
Last data sent
P
A
A
DATA n+x
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
6257A–ATARM–20-Feb-08
A
A
P
P
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