SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 235
SAM7L128
Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L128
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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25.9.9
Register Name:CKGR_PLLR
Access Type:Read-write
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 0 when programming the CKGR_PLLR register.
• DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of Slow Clock cycles x8 before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• STMODE: Start Mode
STMODE must be set at 2 when the PLL is Off
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL + 1.
• 0: 0
0 = Bit 29 must always be programmed to 0 when programming this register.
6257A–ATARM–20-Feb-08
DIV
0
1
2 - 255
STMODE
0
1
2
3
31
23
15
–
7
PMC Clock Generator PLL Register
STMODE
30
22
14
–
6
29
21
13
0
5
Divider Selected
Divider output is 0
Divider is bypassed (DIV=1)
Reserved
Start Mode
Fast Startup
Reserved
Normal Startup
Reserved
28
20
12
–
4
MUL
DIV
AT91SAM7L128/64 Preliminary
27
19
11
–
3
PLLCOUNT
26
18
10
2
MUL
25
17
9
1
24
16
8
0
235
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