SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 369
SAM7L128
Manufacturer Part Number
SAM7L128
Description
Manufacturer
Atmel Corporation
Specifications of SAM7L128
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
36 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
80
Ext Interrupts
80
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
3
Segment Lcd
40
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
460
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
6
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.8 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Figure 30-4. Fractional Baud Rate Generator
30.6.1.4
6257A–ATARM–20-Feb-08
SCK
Reserved
MCK/DIV
MCK
Baud Rate in Synchronous Mode
USCLKS
0
1
2
3
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the
system clock.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the
SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty
cycle on the SCK pin, even if the value programmed in CD is odd.
BaudRate
16-bit Counter
CD
Modulus
=
Control
Baudrate
FP
SelectedClock
------------------------------------- -
CD
=
---------------------------------------------------------------- -
⎛
⎝
8 2 Over
glitch-free
USCLKS = 3
(
logic
FP
SelectedClock
–
SYNC
0
AT91SAM7L128/64 Preliminary
) CD
⎛
⎝
CD
>1
1
0
+
FP
------ -
8
⎞
⎠
⎞
⎠
1
0
OVER
Sampling
Divider
FIDI
0
1
SYNC
SCK
Baud Rate
Sampling
Clock
Clock
369
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