SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 435

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

31.6
Table 31-4.
Notes:
6257A–ATARM–20-Feb-08
0x00 + channel * 0x40 + 0x0C
0x00 + channel * 0x40 + 0x1C
0x00 + channel * 0x40 + 0x2C
0x00 + channel * 0x40 + 0x00
0x00 + channel * 0x40 + 0x04
0x00 + channel * 0x40 + 0x08
0x00 + channel * 0x40 + 0x10
0x00 + channel * 0x40 + 0x14
0x00 + channel * 0x40 + 0x18
0x00 + channel * 0x40 + 0x20
0x00 + channel * 0x40 + 0x24
0x00 + channel * 0x40 + 0x28
Timer Counter (TC) User Interface
1. Channel index ranges from 0 to 2.
2. Read-only if WAVE = 0
Offset
Register Mapping
0xC0
0xC4
0xFC
(1)
Register
Channel Control Register
Channel Mode Register
Reserved
Reserved
Counter Value
Register A
Register B
Register C
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Block Control Register
Block Mode Register
Reserved
AT91SAM7L128/64 Preliminary
TC_CMR
TC_CCR
TC_BCR
TC_BMR
TC_IDR
TC_IMR
TC_IER
TC_RC
TC_CV
TC_RA
TC_RB
TC_SR
Name
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Access
–
(2)
(2)
Reset
–
0
0
0
0
0
0
–
–
0
–
0
–
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