SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 828
SAM3S16C
Manufacturer Part Number
SAM3S16C
Description
Manufacturer
Atmel Corporation
Datasheet
1.SAM3S16C.pdf
(1130 pages)
Specifications of SAM3S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
Max. Operating Frequency
100 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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37.10 CE-ATA Operation
37.10.1
37.10.2
37.10.3
37.10.4
786
786
SAM3S16
SAM3S16
Executing an ATA Polling Command
Executing an ATA Interrupt Command
Aborting an ATA Command
CE-ATA Error Recovery
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is
mapped onto MMC register space.
CE-ATA utilizes five MMC commands:
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC
devices.
If the host needs to abort an ATA command prior to the completion signal it must send a special
command to avoid potential collision on the command line. The SPCMD field of the
HSMCI_CMDR must be set to 3 to issue the CE-ATA completion Signal Disable Command.
Several methods of ATA command failure may occur, including:
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism
may be used for each error event. The recommended error recovery procedure after a timeout
is:
• GO_IDLE_STATE (CMD0): used for hard reset.
• STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be
• FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8 bit access
• RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the
• RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA.
2. Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are set to 0.
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA
2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
• No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
• CRC is invalid for an MMC command or response.
• CRC16 is invalid for an MMC data packet.
• ATA Status register reflects an error by setting the ERR bit to one.
• The command completion signal does not arrive within a host specified time out period.
• Issue the command completion signal disable if nIEN was cleared to zero and the
aborted.
only.
control/status registers.
RW_MULTIPLE_BLOCK (CMD61) response has been received.
with nIEN field set to zero to enable the command completion signal in the device.
11117B–ATARM–18-Oct-11
11117B–ATARM–18-Oct-11
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