SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 23

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.5
7.6
11117B–ATARM–18-Oct-11
Master to Slave Access
Peripheral DMA Controller
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired and shown as “-” in the following table.
Table 7-3.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
Instance Name
Slaves
0
1
2
3
4
USART1
USART0
UART1
UART0
UART1
HSMCI
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
PWM
TWI1
TWI0
PIOA
TWI1
TWI0
DAC
SSC
SPI
SAM3S16 Master to Slave Access
Peripheral DMA Controller
External Bus Interface
Channel T/R
Peripheral Bridge
Internal SRAM
Internal Flash
Internal ROM
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Masters
100 Pins
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Cortex-M3 I/D
Bus
X
X
0
-
-
-
Cortex-M3 S
Bus
X
X
X
1
-
-
SAM3S16
PDC
X
X
X
X
2
-
CRCCU
X
X
X
X
3
-
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