SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 55

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.3.3.15
• Active stack pointer
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
• Thread mode privilege level
Defines the Thread mode privilege level:
0 = privileged
1 = unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CON-
TROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and
exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruc-
tion to set the Active stack pointer bit to 1, see
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This
ensures that instructions after the ISB execute using the new stack pointer. See
11117B–ATARM–18-Oct-11
31
23
15
7
CONTROL register
30
22
14
6
The CONTROL register controls the stack used and the privilege level for software execution
when the processor is in Thread mode. See the register summary in
attributes. The bit assignments are:
29
21
13
5
Reserved
“MSR” on page
28
20
12
4
Reserved
Reserved
Reserved
106.
27
19
11
3
“ISB” on page 104
26
18
10
2
Active Stack
Table 12-2 on page 5
Pointer
25
17
9
1
SAM3S16
Thread Mode
Privilege
Level
24
16
8
0
for its
13