SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 50

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.3.3.6
• N
Negative or less than flag:
0 = operation result was positive, zero, greater than, or equal
1 = operation result was negative or less than.
• Z
Zero flag:
0 = operation result was not zero
1 = operation result was zero.
8
31
23
15
N
7
SAM3S16
Application Program Status Register
30
22
14
Z
6
The PSR bit assignments are:
Access these registers individually or as a combination of any two or all three registers, using
the register name as an argument to the MSR or MRS instructions. For example:
The PSR combinations and attributes are:
Table 12-3.
1.
2.
See the instruction descriptions
tion about how to access the program status registers.
The APSR contains the current state of the condition flags from previous instruction executions.
See the register summary in
Register
PSR
IEPSR
IAPSR
EAPSR
• read all of the registers using PSR with the MRS instruction
• write to the APSR using APSR with the MSR instruction.
The processor ignores writes to the IPSR bits.
Reads of the EPSR bits return zero, and the proces-
29
21
13
C
5
sor ignores writes to the these bits.
Type
RW
RO
RW
RW
PSR register combinations
(1)
(2)
(1), (2)
ICI/IT
EPSR and IPSR
Combination
APSR, EPSR, and IPSR
APSR and IPSR
APSR and EPSR
28
20
12
V
4
ISR_NUMBER
Table 12-2 on page 5
Reserved
“MRS” on page 105
27
19
11
Q
3
for its attributes. The bit assignments are:
and
26
18
10
2
“MSR” on page 106
ICI/IT
Reserved
25
17
9
1
11117B–ATARM–18-Oct-11
for more informa-
ISR_NUMBER
24
16
T
8
0