SAM3S16C Atmel Corporation, SAM3S16C Datasheet - Page 505

• Manufacturer Part Number: SAM3S16C
• Manufacturer: Atmel Corporation

Specifications of SAM3S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 100 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 39
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.5.14
463
463
SAM3S16
SAM3S16
Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can
be write-protected by setting the WPEN bit in the
(PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Pro-
tect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
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“PIO Enable Register” on page 468
“PIO Disable Register” on page 468
“PIO Output Enable Register” on page 469
“PIO Output Disable Register” on page 470
“PIO Input Filter Enable Register” on page 471
“PIO Input Filter Disable Register” on page 471
“PIO Multi-driver Enable Register” on page 476
“PIO Multi-driver Disable Register” on page 477
“PIO Pull Up Disable Register” on page 478
“PIO Pull Up Enable Register” on page 478
“PIO Peripheral ABCD Select Register 1” on page 480
“PIO Peripheral ABCD Select Register 2” on page 481
“PIO Output Write Enable Register” on page 486
“PIO Output Write Disable Register” on page 486
“PIO Pad Pull Down Disable Register” on page 484
“PIO Pad Pull Down Status Register” on page 485
“PIO Parallel Capture Mode Register” on page 497
“PIO Write Protect Mode Register”
11117B–ATARM–18-Oct-11
11117B–ATARM–18-Oct-11