ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 93
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 93 of 960
- Download datasheet (15Mb)
8.6.2.12
8.6.2.13
32142A–12/2011
Management of control endpoints
Multi packet mode and single packet mode.
• Overview
• Control write
Single packet mode is the default mode where one USB packet is managed per bank.
The multi-packet mode allows the user to manage data exceeding the maximum endpoint size
(UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention.
This mode can also be coupled with the ping-pong mode.
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn is irrelevant for control endpoints. The user should
therefore never use it for these endpoints. When read, this value is always zero.
Control endpoints are managed using:
Figure 8-6 on page 94
will not necessarily send a NAK on the first IN token:
• For an OUT endpoint, the EPn_PCKSIZE_BK0/1.MULTI_PACKET_SIZE field should be
• For an IN endpoint, the EPn_PCKSIZE_BK0/1.BYTE_COUNT field should be configured
• The RXSTPI bit: is set when a new SETUP packet is received. This has to be cleared by
• The RXOUTI bit: is set when a new OUT packet is received. This has to be cleared by
• The Transmitted IN Data Interrupt (TXINI) bit: is set when the current bank is ready to accept
• If the user knows the exact number of descriptor bytes that will be read, the status stage can
• Alternatively the bytes can be read until the NAKed IN Interrupt (NAKINI) is triggered,
configured correctly to enable the multi-packet mode. See
endpoints” on page
initialized to 0.
correctly to enable the multi-packet mode.
96. For single packet mode, the BYTE_COUNT should be less than EPSIZE.
firmware in order to acknowledge the packet and to free the bank.
firmware in order to acknowledge the packet and to free the bank.
a new IN packet. This has to be cleared by firmware in order to send the packet.
be predicted, and a zero-length packet can be sent after the next IN token.
notifying that all bytes are sent by the host and that the transaction is now in the status stage.
98. For single packet mode, the MULTI_PACKET_SIZE should be
shows a control write transaction. During the status stage, the controller
See”Multi packet mode for IN endpoints” on page
ATUC64/128/256L3/4U
”Multi packet mode for OUT
93
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