ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 594
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 594 of 960
- Download datasheet (15Mb)
24.6.3
24.6.4
32142A–12/2011
Master, Controller, and Slave Modes
I
2
S Reception and Transmission Sequence
The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), when-
ever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values
written to THR should correspond to the samples from the left and right audio channels for the
successive frames.
The Receive Ready and Transmit Ready bits can be polled by reading the Status Register.
The IISC processor load can be reduced by enabling interrupt-driven operation. The RXRDY
and/or TXRDY interrupt requests can be enabled by writing a one to the corresponding bit in the
Interrupt Enable Register (IER). The interrupt service routine associated to the IISC interrupt
request will then be executed whenever the Receive Ready or the Transmit Ready status bit is
set.
In Master and Controller modes, the IISC provides the Master Clock, the Serial Clock and the
Word Select. IMCK, ISCK, and IWS pins are outputs.
In Controller mode, the IISC Receiver and Transmitter are disabled. Only the clocks are enabled
and used by an external receiver and/or transmitter.
In Slave mode, the IISC receives the Serial Clock and the Word Select from an external master.
ISCK and IWS pins are inputs.
The mode is selected by writing the MODE field of the Mode Register (MR). Since the MODE
field changes the direction of the IWS and ISCK pins, the Mode Register should only be written
when the IISC is stopped, in order to avoid unwanted glitches on the IWS and ISCK pins.
As specified in the I
MSB transmitted first, starting one clock period after the transition on the Word Select line.
Figure 24-2. I
Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the
Serial Clock. The Word Select line indicates the channel in transmission, a low level for the left
channel and a high level for the right channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing
the MR.DATALENGTH field.
If the time slot allows for more data bits than written in the MR.DATALENGTH field, zeroes are
appended to the transmitted data word or extra received bits are discarded. If the time slot
allows for less data bits than written, the extra bits to be transmitted are not sent or the missing
bits are set to zero in the received data word.
Serial Clock ISCK
Word Select IWS
Data ISDI/ISDO
2
S Reception and Transmission Sequence
2
S protocol, data bits are left-adjusted in the Word Select time slot, with the
MSB
Left Channel
ATUC64/128/256L3/4U
LSB
MSB
Right Channel
594
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