ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 247
ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 247 of 960
- Download datasheet (15Mb)
14.5.3
Figure 14-1. PLL with Control Logic and Filters
14.5.3.1
32142A–12/2011
Source
clocks
PLLOSC
PLL Operation
Enabling the PLL
f
REF
Divider
PLLDIV
Input
used in Shutdown mode, PINSEL must be written to one, and XIN32_2 and XOUT32_2 must be
used.
Rev: 1.1.0.0
The device contains one Phase Locked Loop (PLL), which is controlled by the Phase Locked
Loop Interface (PLLIF). The PLL is disabled by default, but can be enabled to provide high fre-
quency source clocks for synchronous or generic clocks. The PLL can use different clock
sources as reference clock, please refer to the “PLL Clock Sources” table in the SCIF Module
Configuration section for details. The PLL output is divided by a multiplication factor, and the
PLL compares the phase of the resulting clock to the reference clock. The PLL will adjust its out-
put frequency until the two compared clocks phases are equal, thus locking the output frequency
to a multiple of the reference clock frequency.
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent the connected digital logic
from receiving a too high frequency and thus become unstable.
The PLL can be configured by writing the PLL Control Register (PLLn). To prevent unexpected
writes due to software bugs, write access to the PLLn register is protected by a locking mecha-
nism, for details please refer to the UNLOCK register description.
Before the PLL is enabled it must be set up correctly. The
selects a source for the reference clock. The PLL Multiply Factor (PLLMUL) and PLL Division
Divider
Output
PLLMUL
Detector
Phase
PLLOPT[0]
VCO
f
vco
1/2
Counter
Lock
ATUC64/128/256L3/4U
PLLOPT[1]
0
1
PLL Oscillator Select field (
f
PLL
Mask
Lock bit
PLL clock
PLLOSC)
247
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