ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 460
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 460 of 960
- Download datasheet (15Mb)
20.6.8.2
Figure 20-35. Slave Node with Peripheral DMA Controller
20.6.9
20.6.10
32142A–12/2011
WRITE BUFFER
DA TA 0
DA TA N
|
|
|
|
Wake-up Request
Bus Idle Time-out
Slave Node Configuration
Peripheral DMA
Controller
In this mode, the Peripheral DMA Controller transfers only data. The user reads the Identifier
from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the
write buffer, while the read buffer contains the data when NACT=SUBSCRIBE.
IMPORTANT: if in slave mode, NACT is already configured correctly as PUBLISH, the LINMR
register must still be written with this value in order to set TXRDY, and to request the corre-
sponding Peripheral DMA Controller write transfer.
Any node in a sleeping LIN cluster may request a wake-up. By writing to the Wakeup Signal
Type bit (LINMR.WKUPTYP), the user can choose to send either a LIN 1.3 (WKUPTYP=1), or a
LIN 2.0 (WKUPTYP=0) compliant wakeup request. Writing a one to the Send LIN Wakeup Sig-
nal bit (CR.LINWKUP), transmits a wakeup, and when completed sets LINTC.
According to LIN 1.3, the wakeup request should be generated with the character 0x80 in order
to impose eight successive dominant bits.
According to LIN 2.0, the wakeup request is issued by forcing the bus into the dominant state for
250µs to 5ms. Sending the character 0xF0 does this, regardless of baud rate.
LIN bus inactivity should eventually cause slaves to time-out and enter sleep mode. LIN 1.3
specifies this to 25000 bit periods, whilst LIN 2.0 specifies 4seconds. For the time-out counter
operation see
Table 20-9.
• Baud rate max = 20 kbit/s -> one bit period = 50µs -> five bit periods = 250µs
• Baud rate min = 1 kbit/s -> one bit period = 1ms -> five bit periods = 5ms
LIN Specification
P eriphe ral
TXRDY
2.0
1.3
bus
Section 20.6.3.8 ”Receiver Time-out” on page
Receiver Time-out Values (RTOR.TO)
CONTROLLER
USART LIN
19 200 bit/s
20 000 bit/s
Baud Rate
1 000 bit/s
2 400 bit/s
9 600 bit/s
-
READ BUFFER
DATA 0
DA TA N
|
|
|
|
25 000 bit periods
Time-out period
ATUC64/128/256L3/4U
4s
Peripheral DMA
444.
Controller
P eripheral
RXRDY
Bus
38 400
76 800
80 000
25 000
4 000
9 600
NACT = SUBSCRIBE
TO
CONTROLLER
USART LIN
460
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