ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 786
ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
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31.7.4
Name:
Access Type:
Offset:
Reset Value:
• DIV: Clock Divider
• CHLEN: Charge Length
• SELEN: Settle Length
32142A–12/2011
31
23
15
7
The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.The
prescaler uses the following formula to generate the sampling clock:
Sampling clock = CLK_CAT / (2(DIV+1))
For the autonomous QTouch sensor and DMATouch sensors, specifies how many sample clock cycles should be used for
transferring charge to the sense capacitor.
For the autonomous QTouch sensor and DMATouch sensors, specifies how many sample clock cycles should be used for
settling after charge transfer.
Autonomous/DMA Touch Configuration Register 0
30
22
14
6
ATCFG0
Read/Write
0x10
0x00000000
29
21
13
5
28
20
12
4
DIV[15:8]
DIV[7:0]
CHLEN
SELEN
27
19
11
3
ATUC64/128/256L3/4U
26
18
10
2
25
17
9
1
24
16
8
0
786
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