ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 352

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

16. Watchdog Timer (WDT)
16.1
16.2
16.3
Figure 16-1. WDT Block Diagram
16.4
32142A–12/2011
OSC32K
Features
Overview
Block Diagram
Product Dependencies
RCSYS
CSSEL
0
1
CEN
Rev: 4.1.0.0
•
•
•
•
•
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The WDT has an internal counter clocked from the system RC oscillator or the 32 KHz crystal
oscillator.
The WDT counter must be periodically cleared by software to avoid a watchdog reset. If the
WDT timer is not cleared correctly, the device will reset and start executing from the boot vector.
In order to use this module, other parts of the system must be configured correctly, as described
below.
Watchdog Timer counter with 32-bit counter
Timing window watchdog
Clocked from system RC oscillator or the 32 KHz crystal oscillator
Configuration lock
WDT may be enabled at reset by a fuse
CLK_CNT
PB
CLK_CNT Domain
PB Clock Domain
32-bit Counter
WDTCLR
CLR
SYNC
ATUC64/128/256L3/4U
WINDOW,
CLEARED
SR
Watchdog
Detector
PSEL, TBAN
EN, MODE,
CTRL
Watchdog
Reset
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