ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 251
ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
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- Download datasheet (15Mb)
32142A–12/2011
only be executed if the Dithering Enable bit (DITHER) in DFLLnCONF has been written to a one.
If DITHER is written to a zero DFLLnLOCKA will never occur. If dithering is enabled, the fre-
quency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER). This clock has to
be set up correctly before enabling dithering. Please refer to the Generic Clocks section for
details.
Figure 14-3. DFLL Closed loop State Diagram
When dithering is enabled the accuracy of the average output frequency of the DFLL will be
higher. However, the actual frequency will be alternating between two frequencies. If a fixed fre-
quency is required, the dithering should not be enabled.
Figure 14-4. DFLL Locking in Closed loop
CLK_DFLL is ready to be used when the DFLLn Synchronization Ready bit (DFLLnRDY) in
PCLKSR is set after enabling the DFLL. However, the accuracy of the output frequency depends
on which locks are set.
For lock times, please refer to the Electrical Characteristics chapter.
DFLLnLOCKC
Calculate
COARSE
Measure
value
f
new
DFLLn
0
frequency
frequency
Target
Initial
1
DFLLnLOCKF
new FINE
Calculate
value
0
DFLLnLOCKC DFLLnLOCKF DFLLnLOCKA
1
Compen-
DITHER
sate for
drift
0
ATUC64/128/256L3/4U
1
DFLLnLOCKA
Calculate
dutycycle
dithering
new
0
1
Compen-
sate for
drift
251
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