ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 781
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 781 of 960
- Download datasheet (15Mb)
31.7
Table 31-3.
32142A–12/2011
Offset
0x0C
0x1C
0x2C
0x3C
0x4C
0x5C
0x6C
0x7C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
0x58
0x60
0x64
0x68
0x70
0x74
0x78
0x80
0x84
0x88
User Interface
CAT Register Memory Map
Autonomous/DMA Touch Configuration Register 0
Autonomous/DMA Touch Configuration Register 1
Autonomous/DMA Touch Configuration Register 2
Autonomous/DMA Touch Configuration Register 3
Acquisition Initiation and Selection Register
Autonomous Touch Current Count Register
Analog Comparator Shift Offset Register 0
Analog Comparator Shift Offset Register 1
Analog Comparator Shift Offset Register 2
Autonomous Touch Pin Selection Register
Spread Spectrum Configuration Register
Autonomous Touch Base Count Register
Touch Group A Configuration Register 0
Touch Group A Configuration Register 1
Touch Group B Configuration Register 0
Touch Group B Configuration Register 1
Matrix Group Configuration Register 0
Matrix Group Configuration Register 1
Matrix Group Configuration Register 2
Discharge Current Source Register
DMATouch State Write Register
DMATouch State Read Register
CSA Resistor Control Register
CSB Resistor Control Register
Matrix Burst Length Register
Interrupt Disable Register
Interrupt Enable Register
Acquired Count Register
Interrupt Mask Register
Status Clear Register
Pin Mode Register 0
Pin Mode Register 1
Pin Mode Register 2
Control Register
Status Register
Register
Register Name
PINMODE0
PINMODE1
PINMODE2
TGACFG0
TGACFG1
TGBCFG0
TGBCFG1
MGCFG0
MGCFG1
MGCFG2
DMATSW
ACOUNT
CSARES
CSBRES
ATCURR
DMATSR
ATCFG0
ATCFG1
ATCFG2
ATCFG3
ATBASE
ATPINS
ACSHI0
ACSHI1
ACSHI2
MBLEN
SSCFG
CTRL
AISR
DICS
SCR
IMR
IER
IDR
SR
ATUC64/128/256L3/4U
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Read-only
Write-only
Read-only
Access
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
-
-
-
-
781
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