ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 442
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 442 of 960
- Download datasheet (15Mb)
20.6.3.4
Figure 20-9. Receiver Status
20.6.3.5
32142A–12/2011
Receiver Operations
Parity
Baud Rate
RXRDY
OVRE
Clock
Read
Write
RHR
RXD
CR
Figure 20-8. Synchronous Mode Character Reception
When a character reception is completed, it is transferred to the Received Character field in the
Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status
Register (CSR.RXRDY) is set. If RXRDY is already set, RHR will be overwritten and the Overrun
Error bit (CSR.OVRE) is set. Reading RHR will clear RXRDY, and writing a one to the Reset
Status bit in the Control Register (CR.RSTSTA) will clear OVRE.
The USART supports five parity modes selected by MR.PAR. The PAR field also enables the
Multidrop mode, see
be a zero if there is an even number of ones in the data character, and if there is an odd number
it will be a one. For odd parity the reverse applies. If space or mark parity is chosen, the parity bit
will always be a zero or one, respectively. See
Table 20-4.
Start
Alphanum
Character
Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
D0
Sampling
R
A
V
D1
Clock
RXD
D2
Parity Bit Examples
D3
0x41
0x56
0x52
Hex
D4
Start
”Multidrop Mode” on page
D5
D6
D0
0100 0001
0101 0110
0101 0010
D7
Parity
Bin
Bit
D1
Stop
Bit
Start
Bit
D2
D0
Odd
D1
1
1
0
D3
Table
443. If even parity is selected, the parity bit will
D2
D3
ATUC64/128/256L3/4U
20-4.
D4
D4
Even
0
0
1
D5
D5
D6
Parity Mode
D7
D6
Mark
Parity
Bit
1
1
1
Stop
Bit
D7
Parity Bit
Space
RSTSTA = 1
0
0
0
Stop Bit
None
-
-
-
442
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