ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 690

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.6.3
28.6.4
28.6.5
28.6.6
32142A–12/2011
Basic operation
Data Format
Data Swapping
Common Mode Offset Control
To convert audio data to a digital bitstream the user must first initialize the ABDACB as
described in
ready to receive new data by setting the Transmit Ready bit in the Status Register (SR.TXRDY).
When the TXRDY bit is set in the Status Register the user has to write new samples to Sample
Data Register 0 (SDR0) and Sample Data Register 1 (SDR1). If the Mono Mode (MONO) bit in
the Control Register (CR) is set, or one of the compact stereo formats are used by configuring
the Data Word Format (DATAFORMAT) in the Control Register, only SDR0 has to be written.
Failing to write to the sample data registers will result in an underrun indicated by the Transmit
Underrun (TXUR) bit in the Status Register (SR.TXUR). When new samples are written to the
sample data registers the TXRDY bit will be cleared.
To increase performance of the system an interrupt handler or DMA transfer can be used to
write new samples to the sample data registers. See
Section 28.6.11
The input data type is two’s complement. The Audio Bitstream DAC can be configured to accept
different audio formats. The format must be configured in the Data Word Format field in the Con-
trol Register. In regular operation data for the two channels are written to the sample data
registers SDR0 and SDR1. If the data format field specifies a format using less than 32 bits, data
must be written right-justified in SDR0 and SDR1. Sign extension into the unused bits is not nec-
essary. Only the 16 most significant bits in the data will be used by the ABDACB. For data
formats larger than 16 bits the least significant bits are ignored. For 8-bit data formats the 8 bits
will be used as the most significant bits in the 16-bit samples, the additional bits will be zeros.
The ABDACB also supports compact data formats for 16- and 8-bit samples. For 16-bit samples
the sample for channel 0 must be written to bits 15 through 0 and the sample for channel 1 must
be written to bits 31 through 16 in SDR0. For 8-bit samples the sample for channel 0 must be
written to bits 7 through 0 and the sample for channel 1 must be written to bits 15 through 8 in
SDR0. SDR1 is not used in this mode. See
When the Swap Channels (SWAP) bit in the Control Register (CR.SWAP) is one, writing to the
Sample Data Register 0 (SDR0) will put the data in Sample Data Register 1 (SDR1). Writing
SDR1 will put the data in SDR0. If one of the two compact stereo formats is used the lower and
upper halfword of SDR0 will be swapped when writing to SDR0.
When the Common Mode Offset Control (CMOC) bit in the Control Register is one the input data
will get a DC value applied to it and the amplitude will be scaled. This will make the common
mode offset of the two corresponding outputs, DAC and DACN, to move away from each other
so that the output signals are not overlapping. The result is that the two signals can be applied to
a differential analog filter, and the difference will always be a positive value, removing the need
for a negative voltage supply for the filter. The cost of doing this a 3dB loss in dynamic range. On
the left side of
sine wave is played when CR.CMOC is zero. The waveform on the right side shows the output
of the differential filter when the two outputs on the left side are used as inputs to the differential
filter.
Figure 28-3
Section
Figure 28-2
for details on interrupt.
show the corresponding outputs when CR.CMOC is one.
28.6.2. When the ABDACB is initialized and enabled it will indicate that it is
one can see the filtered output from the DAC and DACN pins when a
Table 28-5 on page
ATUC64/128/256L3/4U
Section 28.6.10
699.
for details on DMA, and
690