ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 602

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.8.2
Name:
Access Type:
Offset:
Reset Value:
The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK,
and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to dis-
able the IISC before writing a new value into MR.
• IWS24: IWS TDM Slot Width
• IMCKMODE: Master Clock Mode
• IMCKFS: Master Clock to fs Ratio
Table 24-4.
32142A–12/2011
fs Ratio
128 fs
256 fs
192fs
16 fs
32 fs
64 fs
48fs
96fs
IWS24
31
23
15
7
-
-
-
0: IWS slot is 32-bit wide for DATALENGTH=18/20/24-bit
1: IWS slot is 24-bit wide for DATALENGTH=18/20/24-bit
Refer to
0: No Master Clock generated (generic clock is used as ISCK output)
1: Master Clock generated (generic clock is used as IMCK output)
Warning: if IMCK frequency is the same as ISCK, IMCKMODE should not be written as one. Refer to
Clock and Word Select Generation” on page 595
Master Clock frequency is 16*(IMCKFS+1) times the sample rate, i.e. IWS frequency:
Mode Register
IMCKFS
Master Clock to Sample Frequency (fs) Ratio
11
15
Table 24-2, “Slot Length,” on page
0
1
2
3
5
7
IMCKMODE
TXSAME
30
22
14
MR
Read/Write
0x04
0x00000000
6
-
-
TXDMA
29
21
13
5
-
-
595.
TXMONO
28
20
12
and
4
-
Table 24-2, “Slot Length,” on page
DATALENGTH
27
19
11
3
-
IMCKFS
ATUC64/128/256L3/4U
RXLOOP
26
18
10
2
-
595.
RXDMA
25
17
9
1
-
-
Section 24.6.5 ”Serial
RXMONO
MODE
24
16
8
0
-
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