ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 85
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
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- Download datasheet (15Mb)
8.6
8.6.1
8.6.1.1
8.6.1.2
8.6.1.3
8.6.1.4
32142A–12/2011
Functional Description
USB General Operation
Initialization
Interrupts
Frozen clock
Speed control
• Device mode
After a hardware reset, the USBC is in the Reset state. In this state:
After writing a one to USBCON.USBE, the USBC enters device mode in idle state.
Refer to
The USBC can be disabled at any time by writing a zero to USBCON.USBE, this acts as a hard-
ware reset, except that the FRZCLK,bit in USBCON, and the LS bits in UDCON are not reset.
One interrupt vector is assigned to the USBC.
See
See
When the USB clock is frozen, it is still possible to access the following bits: FRZCLK, and USBE
in the USBCON register, and LS in the UDCON register.
When FRZCLK is set, only the asynchronous interrupt can trigger a USB interrupt (see
8.5.4).
When the USBC interface is in device mode, the speed selection is done by the UDCON.LS bit,
connecting an internal pull-up resistor to either DP (full-speed mode) or DM (low-speed mode).
The LS bit shall be written before attaching the device, which can be simulated by clearing the
UDCON.DETACH bit.
• The module is disabled. The USBC Enable bit in the General Control register
• The module clock is stopped in order to minimize power consumption. The Freeze USB Clock
• The USB pad is in suspend mode.
• The internal states and registers of the device are reset.
• The Freeze USB Clock (FRZCLK), USBC Enable (USBE), in USBCON and the Low-Speed
(USBCON.USBE) is reset.
bit in USBCON (USBCON.FRZCLK) is set.
mode bit in the Device General Control register (UDCON.LS) can be written to by software,
so that the user can configure pads and speed before enabling the module. These values are
only taken into account once the module has been enabled and unfrozen.
Section 8.6.2.18
Section 8.5.4
Section 8.6.2
for asynchronous interrupts.
for further details about device interrupts.
for the basic operation of the device mode.
ATUC64/128/256L3/4U
Section
85
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