ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 79
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 79 of 960
- Download datasheet (15Mb)
7.8
32142A–12/2011
Module Configuration
The specific configuration for each PDCA instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 7-6.
Table 7-7.
Table 7-8.
The PDCA and the peripheral modules communicate through a set of handshake signals. The
following table defines the valid settings for the Peripheral Identifier (PID) in the PDCA Periph-
eral Select Register (PSR). The direction is specified as observed from the memory, so RX
means transfers from peripheral to memory, and TX means from memory to peripheral.
Table 7-9.
Feature
Number of channels
Number of performance monitors
Clock Name
CLK_PDCA_HSB
CLK_PDCA_PB
Register
PSR CH 0
PSR CH 1
PSR CH 2
PSR CH 3
PSR CH 4
PSR CH 5
PSR CH 6
PSR CH 7
PSR CH 8
PSR CH 9
PSR CH 10
PSR CH 11
VERSION
PID
0
1
2
PDCA Configuration
PDCA Clocks
Register Reset Values
Peripheral Identity Values
Direction
RX
RX
RX
Peripheral Instance
USART0
USART1
USART2
Description
Clock for the PDCA HSB interface
Clock for the PDCA PB interface
PDCA
12
1
Reset Value
0
1
2
3
4
5
6
7
8
9
10
11
123
ATUC64/128/256L3/4U
Peripheral Register
RHR
RHR
RHR
79
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