ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 592
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 592 of 960
- Download datasheet (15Mb)
24.3
24.4
24.5
24.5.1
24.5.2
32142A–12/2011
Block Diagram
I/O Lines Description
Product Dependencies
I/O lines
Power Management
Figure 24-1. IISC Block Diagram
Table 24-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The IISC pins may be multiplexed with I/O Controller lines. The user must first program the I/O
Controller to assign the desired IISC pins to their peripheral function. If the IISC I/O lines are not
used by the application, they can be used for other purposes by the I/O Controller. It is required
to enable only the IISC inputs and outputs actually in use.
If the CPU enters a sleep mode that disables clocks used by the IISC, the IISC will stop function-
ing and resume operation after the system wakes up from sleep mode.
Bus Bridge
Peripheral
Peripheral
Controller
Controller
Manager
Interrupt
Pin Name
Power
SCIF
DMA
IMCK
ISDO
ISCK
IWS
ISDI
I/O Lines Description
PB clock
Master Clock
Serial Clock
I
Serial Data Input
Serial Data Output
2
IRQ
PB
Rx
S Word Select
Tx
Generic clock
Pin Description
Transmitter
Receiver
Clocks
ATUC64/128/256L3/4U
IISC
Input/Output
Input/Output
IMCK
ISCK
IWS
ISDI
ISDO
Output
Output
Type
Input
592
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