ATmega8HVA Atmel Corporation, ATmega8HVA Datasheet - Page 44

• Manufacturer Part Number: ATmega8HVA
• Manufacturer: Atmel Corporation

Specifications of ATmega8HVA

• Flash (kbytes): 8 Kbytes
• Pin Count: 28
• Max. Operating Frequency: 4 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -20 to 85
• I/o Supply Class: 1.8 to 9.0
• Operating Voltage (vcc): 1.8 to 9.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.2.2
11.2.3
11.2.4
44
ATmega8HVA/16HVA
External Reset
Watchdog Reset
Brown-out Detection
5. When the internal reset goes low, software starts up and loads the VREF calibration reg-
Now the chip can operate normally, but writing to EEPROM in DUVR mode for single cell appli-
cations should be avoided.
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal
reaches the Reset Threshold Voltage – V
MCU after the Time-out period – t
Figure 11-3. External Reset During Operation
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
page 46
Figure 11-4. Watchdog Reset During Operation
ATmega8HVA/16HVA has an On-chip Brown-out Detection (BOD) circuit for monitoring the
V
hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level
should be interpreted as V
REG
isters to get VREF = 1.100V. As the VREF voltage changes, VREG voltage and VFET
DUVR voltage will rise proportionally to VREF.
level during operation by comparing it to a fixed trigger level V
for details on operation of the Watchdog Timer.
FET
BOT+
Table 29-6 on page
= V
TOUT
BOT
– has expired.
+ V
CK
RST
HYST
– on its positive edge, the delay counter starts the
/2 and V
170) will generate a reset, even if the clock is not
BOT-
= V
BOT
- V
BOT
HYST
. The trigger level has a
/2.
TOUT
8024A–AVR–04/08
. Refer to