ATmega8HVA Atmel Corporation, ATmega8HVA Datasheet - Page 144

• Manufacturer Part Number: ATmega8HVA
• Manufacturer: Atmel Corporation

Specifications of ATmega8HVA

• Flash (kbytes): 8 Kbytes
• Pin Count: 28
• Max. Operating Frequency: 4 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -20 to 85
• I/o Supply Class: 1.8 to 9.0
• Operating Voltage (vcc): 1.8 to 9.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

26.2.5
144
ATmega8HVA/16HVA
Reading the Signature Row from Software
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-save sleep mode during periods of low V
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in
is executed within three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the
signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will
auto-clear 6 cycles after writing to SPMCSR, which is locked for further writing during these
cycles. The LPM instruction must be executed within 3 CPU cycles after writing SPMCSR. When
SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
Table 26-1.
Signature Byte Description
Device ID 0, Manufacture ID
Device ID 1, Flash Size
Device ID 2, Device
FOSCCAL
FOSC SEGMENT
Reserved
SLOW RC Period L
SLOW RC Period H
SLOW RC Temp Prediction L
SLOW RC Temp Prediction H
ULP RC FRQ
SLOW RC FRQ
Reserved
BGCCR Calibration Byte @ 25°C
Reserved
BGCRR Calibration Byte @ 25°C
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
used. If a reset occurs while a write operation is in progress, the write operation will be
completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
Table 26-1
(1)
(6)
Signature Row Addressing.
(5)
(2)
(3)
and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction
(4)
CC
reset protection circuit can be
Z-Pointer Address
0CH:0EH
0AH
0BH
0FH
00H
02H
04H
01H
03H
05H
06H
07H
08H
09H
10H
11H
CC
. This will pre-
8024A–AVR–04/08