ATmega8HVA Atmel Corporation, ATmega8HVA Datasheet - Page 143

• Manufacturer Part Number: ATmega8HVA
• Manufacturer: Atmel Corporation

Specifications of ATmega8HVA

• Flash (kbytes): 8 Kbytes
• Pin Count: 28
• Max. Operating Frequency: 4 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -20 to 85
• I/o Supply Class: 1.8 to 9.0
• Operating Voltage (vcc): 1.8 to 9.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

26.2.1
26.2.2
26.2.3
26.2.4
8024A–AVR–04/08
EEPROM Write Prevents Writing to SPMCSR
Setting the Lock Bits from Software
Reading the Fuse and Lock Bits from Software
Preventing Flash Corruption
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
To set the Lock Bits, write the desired data to R0. If bits 1..0 in R0 are cleared (zero), the corre-
sponding Lock bit will be programmed if an SPM instruction is executed within four cycles after
RFLB and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for
future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for read-
ing the Lock bits). For future compatibility it is also recommended to set bit 7..2 in R0 to “1” when
writing the Lock bits. When programming the Lock bits the entire Flash can be read during the
operation.
See
Lock bits affect the Flash access.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction
is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the
value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will
auto-clear 6 cycles after writing to SPMCSR if no SPM instruction is executed within four CPU
cycles. SPMCSR is locked for further writing until it is auto-cleared. The LPM instruction must be
executed within three CPU cycles after writing SPMCSR. When RFLB and SPMEN are cleared,
LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and
SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. Refer to
detailed description and mapping of the Fuse Low byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
Bit
R0
Bit
Rd
Bit
Rd
Table 27-1 on page 149
FLB7
7
1
7
7
–
CC
FLB6
, the Flash program can be corrupted because the supply voltage is
6
1
6
6
–
and
FLB5
Table 27-2 on page 149
5
1
5
5
–
FLB4
4
1
4
–
4
FLB3
3
1
3
–
3
ATmega8HVA/16HVA
for how the different settings of the
FLB2
2
1
2
–
2
Table 27-4 on page 150
FLB1
LB2
LB2
1
1
1
FLB0
LB1
LB1
0
0
0
for a
143