ATmega8HVA Atmel Corporation, ATmega8HVA Datasheet - Page 131

• Manufacturer Part Number: ATmega8HVA
• Manufacturer: Atmel Corporation

Specifications of ATmega8HVA

• Flash (kbytes): 8 Kbytes
• Pin Count: 28
• Max. Operating Frequency: 4 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -20 to 85
• I/o Supply Class: 1.8 to 9.0
• Operating Voltage (vcc): 1.8 to 9.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

23.9.6
23.9.7
23.9.8
8024A–AVR–04/08
BPSCD – Battery Protection Short-circuit Detection Level Register
BPDOCD – Battery Protection Discharge-Over-current Detection Level Register
BPCOCD – Battery Protection Charge-Over-current Detection Level Register
• Bits 7:0 – SCDL7:0: Short-circuit Detection Level
These bits sets the R
as defined in
Note:
• Bits 7:0 – DOCDL7:0: Discharge Over-current Detection Level
These bits sets the R
Table 23-5 on page
Note:
• Bits 7:0 –COCDL7:0: Charge Over-current Detection Level
These bits sets the R
Table 23-5 on page
Note:
Bit
(0xF5)
Read/Write
Initial Value
Bit
(0xF6)
Read/Write
Initial Value
Bit
(0xF7)
Read/Write
Initial Value
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPSCD register is written. Any
writing to the BPSCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPDOCD register is written. Any
writing to the BPDOCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCOCD register is written. Any
writing to the BPCOCD register during this period will be ignored.
Table 23-5 on page
R/W
R/W
R/W
7
1
7
1
7
1
132.
132.
SENSE
SENSE
SENSE
R/W
R/W
R/W
6
1
6
1
6
1
voltage level for detection of Short-circuit in the discharge direction,
voltage level for detection of Discharge Over-current, as defined in
voltage level for detection of Charge Over-current, as defined in
132.
R/W
R/W
R/W
5
1
5
1
5
1
R/W
R/W
R/W
4
1
4
1
4
1
DOCDL[7:0]
COCDL[7:0]
SCDL[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
ATmega8HVA/16HVA
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
1
1
1
1
1
R/W
R/W
R/W
0
1
0
1
0
1
BPDOCD
BPCOCD
BPSCD
131