ATmega8HVA Atmel Corporation, ATmega8HVA Datasheet - Page 152

• Manufacturer Part Number: ATmega8HVA
• Manufacturer: Atmel Corporation

Specifications of ATmega8HVA

• Flash (kbytes): 8 Kbytes
• Pin Count: 28
• Max. Operating Frequency: 4 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -20 to 85
• I/o Supply Class: 1.8 to 9.0
• Operating Voltage (vcc): 1.8 to 9.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

27.6.1
152
ATmega8HVA/16HVA
Serial Programming Algorithm
Figure 27-1. Serial Programming and Verify.
Table 27-8.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on OSCSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2.2 CPU clock cycles for f
High: > 2.2 CPU clock cycles for f
When writing serial data to the ATmega8HVA/16HVA, data is clocked on the rising edge of SCK.
When reading data from the ATmega8HVA/16HVA, data is clocked on the falling edge of SCK.
See
To program and verify the ATmega8HVA/16HVA in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
”Serial Programming” on page 172
Symbol
MOSI
MISO
SCK
Pin Mapping Serial Programming
MOSI
MISO
SCK
CC
and GND while RESET and SCK are set to “0”. In some sys-
Pins
PB1
PB2
PB3
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
RESET
GND
for timing details.
I/O
O
I
I
VCC
+3.0 - 4.5V
Table 27-10 on page
Serial Data out
Serial Data in
Description
Serial Clock
ck
ck
>= 12 MHz
>= 12 MHz
8024A–AVR–04/08
154):