ATmega8HVA Atmel Corporation, ATmega8HVA Datasheet - Page 135

• Manufacturer Part Number: ATmega8HVA
• Manufacturer: Atmel Corporation

Specifications of ATmega8HVA

• Flash (kbytes): 8 Kbytes
• Pin Count: 28
• Max. Operating Frequency: 4 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -20 to 85
• I/o Supply Class: 1.8 to 9.0
• Operating Voltage (vcc): 1.8 to 9.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

24. FET Control
24.1
24.1.1
8024A–AVR–04/08
Overview
FETs disabled during reset
The FET control is used to enable and disable the Charge FET and Discharge FET. Normally,
the FETs are enabled and disabled by SW writing to the FET Control and Status Register
(FCSR). However, the autonomous Battery Protection circuitry will if necessary override SW set-
tings to protect the battery cells from too high Charge- or Discharge currents. Note that the CPU
is never allowed to enable a FET that is disabled by the battery protection circuitry. The FET
control is shown in
If Current Protection is activated by the Battery Protection circuitry both the Charge-FET and
Discharge FET will be disabled by hardware. When the protection disappears the Current Pro-
tection Timer will ensure a hold-off time of 1 second before software can re-enable the external
FETs.
If C-FET is disabled and D-FET enabled, discharge current will run through the body-drain diode
of the C-FET and vice versa. To avoid the potential heat problem from this situation, software
must ensure that D-FET is not disabled when a charge current is flowing, and that C-FET is not
disabled when a discharge current is flowing.
If charging deeply over-discharged cells, the FET driver must be operated in the Deep Under-
voltage Recovery mode. When the cell voltage raises to an acceptable level, Deep Under-volt-
age Recovery mode should be disabled by software by setting the FCSR (DUVRD bit). To avoid
that C-FET is opened while current protection is active, DUVR mode is automatically disabled by
hardware, in this case.
Figure 24-1. FET Control Block Diagram
During reset, both FETs will be disabled immediately and the chip will exit from DUVR mode. It is
important to notice that a reset will lead to an immediate disabling of the FETs regardless of the
Battery Protection parameter settings. A BOD reset may occur as a result of a short-circuit con-
dition. Depending on the selected Battery Protection Timing, actual current consumption and
dimensioning of CREG, a BOD reset may occur before the Battery Protection delay timing has
expired, causing the FETs to be disabled.
Power-off Mode
BATTERY_PROTECTION
Figure
24-1.
Register
Control
Status
FET
and
Current Protection
Timer
DUVRD
CFE
DFE
ATmega8HVA/16HVA
DISCHARGE_EN
CHARGE_EN
DUVR_OFF
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