ATmega8HVA Atmel Corporation, ATmega8HVA Datasheet - Page 43

• Manufacturer Part Number: ATmega8HVA
• Manufacturer: Atmel Corporation

Specifications of ATmega8HVA

• Flash (kbytes): 8 Kbytes
• Pin Count: 28
• Max. Operating Frequency: 4 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 3
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -20 to 85
• I/o Supply Class: 1.8 to 9.0
• Operating Voltage (vcc): 1.8 to 9.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Figure 11-2. Normal Start-up Sequence in Power-off.
8024A–AVR–04/08
1. The charger voltage pulls the BATT pin above the Power-on Threshold Voltage (V
2. When V
3. The internal reset is held high after POR reset goes low for a time given by t
4. As soon as the internal reset goes low, the chip will start operating in DUVR mode (for
VREG starts to rise. The POR reset will go high while VREG is rising and initiate the
internal reset state of the chip. The external FETs are initially switched off.
”System Control and Reset” on page
isters will be reset to their default values. The VREG and BOD levels are both referenced
to the VREF voltage. In reset all these voltage levels will therefore have default values.
Both FETs are switched completely off in this state.
details on DUVR mode, see
on page 137
gate voltage of the Charge FET to get a voltage at the VFET pin given by the VFET level
specified in
that DUVR mode will only regulate the VFET voltage as long as the cell voltage is lower
than the VFET_DUVR level. For high cell voltages, DUVR mode will not have any impact.
DUVR mode may be disabled by SW as soon as the chip enters ACTIVE mode.
BATT
Table 29-5 on page
rises above V
and application note AVR354). In DUVR mode the FET driver controls the
POT
”DUVR – Deep Under-Voltage Recovery Mode operation”
, ATmega8HVA/16HVA turns on the Voltage Regulator and
170. This causes the BATT voltage to decrease. Note
41. While the chip is in reset, VREF calibration reg-
4/8/16/32/64/128/256/512 ms
ATmega8HVA/16HVA
TOUT
, see
POT
).
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