C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 35
C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground pad.
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Dimension
calculated based on a Fabrication Allowance of 0.05 mm.
metal pad is to be 60 m minimum, all the way around the pad.
good solder paste release.
Components.
C1
C2
X1
e
Table 4.6. QFN-40 Landing Diagram Dimensions
5.80
5.80
0.15
Min
Figure 4.6. QFN-40 Landing Diagram
0.50 BSC
Max
5.90
5.90
0.25
Rev. 1.2
Dimension
X2
Y1
Y2
C8051F50x/F51x
4.10
0.75
4.10
Min
Max
4.20
0.85
4.20
35
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