C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 292

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
27.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
292
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
W
P
M
Figure 27.5. PCA Software Timer Mode Diagram
1
6
n
x
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
0 0
C
N
A
P
n
M
A
T
n
O
G
T
n
0 0
W
M
P
n
E
C
C
F
n
x
Enable
PCA
Timebase
Rev. 1.2
PCA0CPLn
PCA0L
16-bit Comparator
PCA0CPHn
PCA0H
Match
C
F
C
R
PCA0CN
C
C
F
2
0
1
C
C
F
1
C
C
F
0
C
C
F
2
C
C
F
1
C
C
F
0
PCA Interrupt