C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 152

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
SFR Definition 18.2. EMI0CF: External Memory Configuration
SFR Address = 0xB2; SFR Page = 0x0F
152
Name
Reset
7:5
3:2
1:0
Bit
Type
4
Bit
EALE[1:0] ALE Pulse-Width Select Bits.
EMD[1:0]
Unused
Name
EMD2
7
0
Read = 000b; Write = Don’t Care.
EMIF Multiplex Mode Select Bit.
0: EMIF operates in multiplexed address/data mode
1: EMIF operates in non-multiplexed mode (separate address and data pins)
EMIF Operating Mode Select Bits.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to
on-chip memory space
01: Split Mode without Bank Select: Accesses below the 4 kB boundary are directed
on-chip. Accesses above the 4 kB boundary are directed off-chip. 8-bit off-chip MOVX
operations use current contents of the Address high port latches to resolve the upper
address byte. To access off chip space, EMI0CN must be set to a page that is not con-
tained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 4 kB boundary are directed on-
chip. Accesses above the 4 kB boundary are directed off-chip. 8-bit off-chip MOVX
operations uses the contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to
the CPU.
These bits only have an effect when EMD2 = 0.
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
6
0
5
0
EMD2
Rev. 1.2
4
0
R/W
Function
3
0
EMD[1:0]
2
0
1
1
EALE[1:0]
0
1