C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 249
C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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SFR Definition 24.2. SMOD0: Serial Port 0 Control
SFR Address = 0xA9; SFR Page = 0x00
Reset
Name
Bit
6:5 S0PT[1:0] Parity Type Select Bits.
3:2 S0DL[1:0] Data Length.
Type
7
4
1
0
Bit
MCE0
Name
XBE0
SBL0
PE0
MCE0
R/W
7
0
Multiprocessor Communication Enable.
0: RI0 will be activated if stop bit(s) are 1.
1: RI0 will be activated if stop bit(s) and extra bit are 1. Extra bit must be enabled using
XBE0.
00: Odd Parity
01: Even Parity
10: Mark Parity
11: Space Parity.
Parity Enable.
This bit enables hardware parity generation and checking. The parity type is selected
by bits S0PT[1:0] when parity is enabled.
0: Hardware parity is disabled.
1: Hardware parity is enabled.
00: 5-bit data
01: 6-bit data
10: 7-bit data
11: 8-bit data
Extra Bit Enable.
When enabled, the value of TBX0 will be appended to the data field
0: Extra Bit is disabled.
1: Extra Bit is enabled.
Stop Bit Length.
0: Short—stop bit is active for one bit time
1: Long—stop bit is active for two bit times (data length = 6, 7, or 8 bits), or 1.5 bit times
(data length = 5 bits).
R/W
6
0
S0PT[1:0]
R
5
0
PE0
R/W
Rev. 1.2
4
0
Function
R/W
3
1
S0DL[1:0]
C8051F50x/F51x
R/W
2
1
XBE0
R/W
1
0
SBL0
R/W
0
0
249
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