C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 230

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 23.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “26. Timers” on page 265.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 23.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 23.2.
Figure 23.4 shows the typical SCL generation described by Equation 23.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 23.1.
230
Timer Source
Overflows
SCL
LOW
T
Equation 23.1. Minimum SCL High and Low Times
. The actual SCL output may vary due to other devices on the bus (SCL may be
Low
SMBCS1
0
0
1
1
T
Figure 23.4. Typical SMBus SCL Generation
HighMin
Table 23.1. SMBus Clock Source Selection
Equation 23.2. Typical SMBus Bit Rate
BitRate
SMBCS0
0
1
0
1
=
T
High
T
LowMin
=
f
-------------------------------------------------
ClockSourceOverflow
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
Rev. 1.2
=
-------------------------------------------------
f
ClockSourceOverflow
3
1
SCL High Timeout
HIGH
is typically