C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 182

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
20.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals.
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Port 4 on the C8051F500/1/4/5 and
C8051F508/9-F510/1 is a digital-only Port. Any pins to be used as Comparator or ADC inputs should be
configured as an analog inputs. When a pin is configured as an analog input, its weak pullup, digital driver,
and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins
configured as digital inputs may still be used by analog peripherals; however this practice is not recom-
mended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
182
P o rt
S p e cia l
F u n ctio n
S ig n a ls
P IN I/O
UART _T X
UART _RX
CAN_T X
CAN_RX
S CK
M IS O
M O S I
NS S
S DA
S CL
CP 0
CP 0A
CP 1
CP 1A
S YS CL K
CEX 0
CEX 1
CEX 2
CEX 3
CEX 4
CEX 5
ECI
T 0
T 1
L IN_T X
L IN_RX
(PnMDOUT).
0
0
1
1
P 0S KIP [0:7]
2
1
Figure 20.4. Crossbar Priority Decoder in Example Configuration
3
0
P 0
4
0
5
1
6
0
7
0
0
0
1
0
*NS S Is only pinned out in 4-wire S P I M ode
P 1S KIP [0:7]
2
0
3
0
P 1
4
0
5
0
6
0
7
0
0
0
Rev. 1.2
1
0
P 2S KIP [0:7]
2
0
3
0
P 2
4
0
5
0
6
0
7
0
0
0
1
0
available on the 48-pin
P 3.1-P 3.7, P 4.0 only
and 40-pin pac k ages
P 3S KIP [0:7]
2
0
3
0
P 3
4
0
5
0
6
0
7
0
0
1
available on the 48-
P 4.1-P 4.7 only
2
pin pac k ages
3
P 4
4
5
6
7