C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 214

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
LIN Register Definition 21.7. LIN0ERR: LIN0 Error Register
Indirect Address = 0x0A
214
Name
Reset
7:5
Bit
Type
4
3
2
1
0
Bit
BITERR
SYNCH
Unused
Name
PRTY
TOUT
CHK
R
7
0
Read = 000b; Write = Don’t Care
Synchronization Error Bit (slave mode only).
0: No error with the SYNCH FIELD has been detected.
1: Edges of the SYNCH FIELD are outside of the maximum tolerance.
Parity Error Bit (slave mode only).
0: No parity error has been detected.
1: A parity error has been detected.
Timeout Error Bit.
0: A timeout error has not been detected.
1: A timeout error has been detected. This error is detected whenever one of the fol-
lowing conditions is met:
•
•
•
•
Checksum Error Bit.
0: Checksum error has not been detected.
1: Checksum error has been detected.
Bit Transmission Error Bit.
0: No error in transmission has been detected.
1: The bit value monitored during transmission is different than the bit value sent.
R
6
0
The master is expecting data from a slave and the slave does not respond.
The slave is expecting data but no data is transmitted on the bus.
A frame is not finished within the maximum frame length.
The application does not set the DTACK bit (LIN0CTRL.4) or STOP bit
(LIN0CTRL.7) until the end of the reception of the first byte after the identifier.
R
5
0
SYNCH
Rev. 1.2
R
4
0
Function
PRTY
R
3
0
TOUT
R
2
0
CHK
R
1
0
BITERR
R
0
0