C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 206
C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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C8051F50x/F51x
1. Check the DONE bit (LIN0ST.0) and the ERROR bit (LIN0ST.2).
2. If performing a master receive operation and the transfer was successful, read the received data from
3. If the transfer was not successful, check the error register to determine the kind of error. Further error
4. Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
21.4. LIN Slave Mode Operation
When the device is configured for slave mode operation, it must wait for a command from a master node.
Access from the firmware to the data buffer and ID registers of the LIN controller is only possible when a
data request is pending (DTREQ bit (LIN0ST.4) is 1) and also when the LIN bus is not active (ACTIVE bit
(LIN0ST.7) is set to 0).
The LIN controller in slave mode detects the header of the message frame sent by the LIN master. If slave
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.
The LIN controller configured for slave mode will generated an interrupt in one of three situations:
1. After the reception of the IDENTIFIER FIELD
2. When an error is detected
3. When the message transfer is completed.
The application should perform the following steps when an interrupt is detected:
1. Check the status of the DTREQ bit (LIN0ST.4). This bit is set when the IDENTIFIER FIELD has been
2. If DTREQ (LIN0ST.4) is set, read the identifier from LIN0ID and process it. If DTREQ (LIN0ST.4) is not
3. Set the TXRX bit (LIN0CTRL.5) to 1 if the current frame is a transmit operation for the slave and set to
4. Load the data length into LIN0SIZE.
5. For a slave transmit operation, load the data to transmit into the data buffer.
6. Set the DTACK bit (LIN0CTRL.4). Continue to step 10.
7. If DTREQ (LIN0ST.4) is not set, check the DONE bit (LIN0ST.0). The transmission was successful if the
8. If the transmission was successful and the current frame was a receive operation for the slave, load the
9. If the transmission was not successful, check LIN0ERR to determine the nature of the error. Further
10.Set the RSTINT (LIN0CTRL.3) and RSTERR bits (LIN0CTRL.2) to reset the interrupt request and the
In addition to these steps, the application should be aware of the following:
1. If the current frame is a transmit operation for the slave, steps 1 through 5 must be completed during
2. If the current frame is a receive operation for the slave, steps 1 through 5 have to be finished until the
3. The LIN controller does not directly support LIN Version 1.3 Extended Frames. If the application detects
206
the data buffer.
handling has to be done by the application.
error flags.
received.
set, continue to step 7.
0 if the current frame is a receive operation for the slave.
DONE bit is set.
received data bytes from the data buffer.
error handling has to be done by the application.
error flags.
the IN-FRAME RESPONSE SPACE. If it is not completed in time, a timeout will be detected by the
master.
reception of the first byte after the IDENTIFIER FIELD. Otherwise, the internal receive buffer of the LIN
controller will be overwritten and a timeout error will be detected in the LIN controller.
an unknown identifier (e.g. extended identifier), it has to write a 1 to the STOP bit (LIN0CTRL.7) instead
Rev. 1.2
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