C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 201

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

21. Local Interconnect Network (LIN)
Important Note: This chapter assumes an understanding of the Local Interconnect Network (LIN) proto-
col. For more information about the LIN protocol, including specifications, please refer to the LIN consor-
tium (http://www.lin-subbus.org).
LIN is an asynchronous, serial communications interface used primarily in automotive networks. The Sili-
con Laboratories LIN controller is compliant to the 2.1 Specification, implements a complete hardware LIN
interface and includes the following features:



Note: The minimum system clock (SYSCLK) required when using the LIN controller is 8 MHz.
The LIN controller has four main components:




Selectable Master and Slave modes.
Automatic baud rate option in slave mode.
The internal oscillator is accurate to within 0.5% of 24 MHz across the entire temperature range and for
VDD voltages greater than or equal to the minimum output of the on-chip voltage regulator, so an
external oscillator is not necessary for master mode operation for most systems.
LIN Access Registers—Provide the interface between the MCU core and the LIN controller.
LIN Data Registers—Where transmitted and received message data bytes are stored.
LIN Control Registers—Control the functionality of the LIN interface.
Control State Machine and Bit Streaming Logic—Contains the hardware that serializes messages and
controls the bus timing of the controller.
RX
TX
Indirectly Addressed Registers
Registers
LIN Data
Control State Machine
LIN Controller
Figure 21.1. LIN Block Diagram
LIN Control
Registers
Rev. 1.2
C8051F50x/F51x
8051 MCU Core
LIN0ADR
C8051F500/2/4/6
LIN0DAT
LIN0CF
201