PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 733

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
5.19.1 Hard Reset
5.19.2 Soft Reset
5.17 Statistics Counters
5.18 Status Vectors
5.19 Reset
In Ethernet applications generally, many counters that keep Ethernet traffic statistics
must be maintained. There are a number of standards specifying such counters, such
as IEEE Std 802.3 / Clause 30. Other standards are RFC 2665 and RFC 2233.
The approach taken here is as follows: by default, all counters are implemented in
software. With the help of the StatusInfo field in the packet status word, many of the
important statistics events listed in the standards can be counted by software.
Currently, no counters are added in hardware.
A transmit status vector and a receive status vector are available in registers TSV0,
TSV1, and RSV. These registers can be polled with software. Normally, they are of
limited use, because the communication between driver software and Ethernet
module takes place primarily through the packet descriptors. Statistical events are
counted by software in the device driver. However, these transmit and receive status
vectors are made visible for debug purposes. The values in these registers are simple
copies of the transmit and receive status vectors as produced by the MII Interface.
They are valid as long as the status vectors are valid, and should typically only be
read when the transmit and receive processes are halted.
The TSV0, TSV1 and RSV registers are defined in
The LAN100 has a hard reset input and several soft resets which can be activated by
setting the appropriate bits in its registers. All registers in the LAN100 have a reset
value of 0 unless specified differently in
The LAN100 module experiences a hard reset when the PNX15xx Series is reset.
After a hard reset, all register values in the software view will be set to their default
value as specified in
Parts of the LAN100 can be reset by software by setting bits in the Command register
and the MAC1 configuration register.
The MAC1 register has six different reset bits:
•
•
SOFT_RESET: Setting this bit will put all components in the MII Interface in the
reset state except for the MII Interface registers (in address locations 72 0000 to
72 00FC). The soft reset bit defaults to 1, and must be cleared after a hardware
reset to enable the MII Interface.
SIMULATION_RESET: Setting this bit resets the random number generator in the
Transmit Function. The value after a hard reset is 0.
Rev. 2 — 1 December 2004
Section
Chapter 23: LAN100 — Ethernet Media Access Controller
3.2.
Section
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
3.2.
Section
PNX15xx Series
3.2.
23-71