PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 530

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 6: Endian Ordering of Audio Data in Main Memory
12NC 9397 750 14321
Product data sheet
Operating
Modes
16-bit stereo
- big endian
32-bit mono -
little endian
32-bit mono -
big endian
32-bit stereo
- little endian
32-bit stereo
- big endian
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3.6 Memory Buffers and Capture
3.7 Data Bus Latency and HBE
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The Audio Input unit hardware implements a double buffering scheme to ensure that
no samples are lost, even if the chip level controller is highly loaded and slow to
respond to interrupts. The software assigns buffers by writing a base address and
size to the MMIO control fields (see
In 16-bit capture modes, the sixteen MSBits of the serial-to-parallel converter output
data are written to memory. In 32-bit capture modes, all bits of the parallel data are
written to memory. If SIGN_CONVERT is set to one, the MSB of the data is inverted,
which is equivalent to translating from two’s complement to offset binary
representation. This allows the use of an external two’s complement 16-32 bit A/D
converter to generate 16-32 bit unsigned samples.
Remark: The Audio In hardware does not generate A-law or -law data formats. If
such formats are desired, additional processing is necessary, via software, to convert
from 16-bit linear data to A-law or -law data.
Audio In uses a 128-byte buffer to capture the audio input samples. When 64-bytes of
space is full, the next incoming samples are continuously stored in the remaining
64-byte space while the adapter issues DMA request for the first 64 bytes of data.
Under normal operation, the first 64-bytes worth data gets written to memory while
the second 64-bytes worth data is being filled up. This normal operation will be
maintained as long as the data bus arbiter is set to guarantee a latency for Audio In
that matches the incoming audio samples rate.
Given a sample rate f
latency should be at most 16*T nSec in the case of 16 bit samples and 8T nSec in the
case of 32 bit samples, for 2 audio channels. Similarly for 4 channels (8T, 4T), 6
channels (16T/3, 8T/3) and 8 channels (4T, 2T) respectively. If this max latency is not
satisfied, the HBE (Bandwidth Error) condition will result. This error flag gets set
when the 128-byte buffer is full and a new sample arrives for that buffer. Thus HBE
error condition occurs when the adapter is unable to transfer data from its FIFO to
memory in time. Hence the adapter FIFO gets full and is not able to accommodate
valid data coming from the Audio In block. This results in an HBE condition.
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Rev. 2 — 1 December 2004
s
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, and an associated sample interval T (in nSec), the bus
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…Continued
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Section 4. on page
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© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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16-15).
PNX15xx Series
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Chapter 16: Audio Input
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Table 7
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16-11