PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 638

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 31: PanicControl
Table 32: EngineConfig
12NC 9397 750 14321
Product data sheet
Bit
Offset 0x04 F804
31:8
7:0
Bit
Offset 0x04 F808
31:11
10
9
8
7:3
Symbol
Reserved
RST
Symbol
Reserved
IRQ_CLR
BMODE
IRQ_EN
Reserved
PanicControl
EngineConfig
This register is currently used to reset the state machines in the drawing engine. It
does not reset any other registers in the Engine.
Acces
s
W
Acces
s
R/W
R/W
R/W
Value
-
Value
0
0
0
Rev. 2 — 1 December 2004
Description
Used to reset the state machines in the Drawing Engine. Writing
0x0000_0001 to this register will halt the Drawing Engine and place
it in an idle state. Writing 0x0000_0000 will allow the DE to be
reprogrammed and resume normal operation. It may be necessary
for software to implement a delay between setting the RST signal to
1 and resetting it to 0.
Description
IRQ_CLR (bit 10) is a self-clearing bit used to reset Drawing Engine
IRQ flip-flop. The IRQ flip-flop is set when the DEBusy bit in the
EngineStatus register transitions from 1 to 0. It is cleared under
software control by setting IRQ_CLR to 1. See BMODE for a
description of DEBusy.
BMODE selects between two slightly different behaviors of DEBusy
and DEDone (EngineStatus register).
0=the DEBusy bit is set to 1 when the BLT/vector state machine
becomes active i.e., a drawing operation is starting. The bit is
cleared only when the state machine is idle, all memory writes are
completed, and the command FIFO is empty.
1=the DEBusy bit is set whenever the BLT/vector state machine is
active OR the command FIFO is not empty. The DEBusy bit will be
cleared when the engine is idle AND the command FIFO is empty.
Note that in this mode, the Draw Engine will go busy whenever a
register is loaded. Using interrupts can be tricky in this mode.
IRQ_EN (bit 8) is used to enable the interrupt signal leaving the
Drawing Engine module. When IRQ_EN is set to a 1, the interrupt
signal is enabled. When set to 0, the interrupt signal leaving the
Drawing Engine is masked. The IRQ_EN does not affect the actual
IRQ flip-flop. It merely masks the IRQ bit leaving the module.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 20: 2D Drawing Engine
PNX15xx Series
20-29