PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 706

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
While issuing the descriptor read commands, the Tx(Rt) DMA manager also begins
to write the transmission status. The status write command address will be taken
from the Tx(Rt)Status register; the block size will be 3 statuses * 1 double words = 3.
After transmitting each fragment of the packet, the Tx(Rt) DMA will write the status of
the fragment’s transmission. Statuses for all but the last fragment in the packet will be
written as soon as the data in the packet has been accepted by the Tx(Rt) DMA
manager. The status for the last fragment in the packet will only be written after the
transmission has completed on the Ethernet connection.
The Tx(Rt) DMA manager checks if status write data has been committed to memory.
Only then are the Tx(Rt)ConsumeIndex updated and the interrupt flags forwarded to
the IntStatus register. The LAN100 tags transmit statuses continuously but does not
necessarily tag every status individually.
Since the Interrupt bit in the descriptor of the last fragment is set, after committing
status of the last fragment to memory, the LAN100 will trigger a Tx(Rt)DoneInt
interrupt which triggers the device driver to inspect the status information.
In this example, the device driver cannot add new descriptors as long as the LAN100
has incremented the Tx(Rt)ConsumeIndex because the descriptor array is full (even
though one descriptor is not programmed yet (see
Only after committing the status for the first fragment to memory and updating the
Tx(Rt)ConsumeIndex to 1 can the device driver program the next (the fourth)
descriptor. The fourth descriptor can be programmed before completely transmitting
the first packet.
In this example the hardware adds the CRC. If the device driver software adds the
CRC, the CRC trailer can be considered another packet fragment which can be
added by doing another gather DMA operation.
Rev. 2 — 1 December 2004
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Section 5.2.4 on page
PNX15xx Series
23-35).
23-44