PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 330

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 8: Register Summary
12NC 9397 750 14321
Product data sheet
Offset
0x06 5000
0x06 5004
0x06 5008
0x06 5010
0x06 5014
0x06 5018
0x06 5080
0x06 5084
0x06 5088
0x06 50C0
0x06 50C4
0x06 50D0
0x06 50D4
0x06 5100
0x06 5104
0x06 5108
0x06 510C
0x06 5110
0x06 5114
0x06 511C
0x06 5120
0x06 5124
0x06 5128
0x06 512C
0x06 5180
0x06 5184
0x06 5188
Symbol
IP_2031_CTL
DDR_DEF_BANK_SWITCH
AUTO_HALT_LIMIT
RANK0_ADDR_LO
RANK0_ADDR_HI
RANK1_ADDR_HI
DDR_MR
DDR_EMR
DDR_PRECHARGE_BIT
RANK0_ROW_WIDTH
RANK0_COLUMN_WIDTH
RANK1_ROW_WIDTH
RANK1_COLUMN_WIDTH
DDR_TRCD
DDR_TRC
DDR_TWTR
DDR_TWR
DDR_TRAS
DDR_TRRD
DDR_TRFC
DDR_TMRD
DDR_TCAS
DDR_RF_PERIOD
ARB_CTL
ARB_HRT_WINDOW
ARB_CPU_WINDOW
DDR_TRP
5.1 Register Summary
Turning the DDR controller into halt mode, programming MMIO registers while in halt
mode, and un-halting the DDR controller when the MMIO registers have been
programmed, is the suggested series of actions to change MMIO register values of a
started DDR controller.
The offsets reported in the following table are absolute offset with respect to the
MMIO_BASE value.
•
•
observe the performance of the DDR SDRAM Controller
observe specifics about errors
Rev. 2 — 1 December 2004
Description
DDR GENERAL CONTROL
DDR BANK SWITCH ADDRESSING
DDR AUTO HALT LIMIT
DDR RANK0 ADDRESS LOW LIMIT
DDR RANK0 ADDRESS HIGH LIMIT
DDR RANK1 ADDRESS HIGH LIMIT
DDR MODE REGISTER
DDR EXTEND MODE REGISTER
DDR PRECHARGE BIT FIELD
DDR RANK0 ROW BIT WIDTH
DDR RANK0 COLUMN BIT WIDTH
DDR RANK1 ROW BIT WIDTH
DDR RANK1 COLUMN BIT WIDTH
DDR ACTIVE to READ or WRITE DELAY
DDR ACTIVE to ACTIVE/AUTO REFRESH DELAY
DDR INTERNAL WRITE to READ COMMAND DELAY
DDR WRITE RECOVERY TIME
DDR PRECHARGE COMMAND PERIOD
DDR ACTIVE to PRECHARGE COMMAND PERIOD
DDR ACTIVE BANK A to ACTIVE BANK B COMMAND
DDR AUTO REFRESH COMMAND PERIOD
DDR LOAD MODE REGISTER COMMAND CYCLE
DDR CAS READ LATENCY
DDR REFRESH PERIOD
DDR ARBITER CONTROL
DDR ARBITER HARD REAL TIME WINDOW
DDR ARBITER CPU WINDOW
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
9-24