PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 326

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
4. Timing Diagrams and Tables
12NC 9397 750 14321
Product data sheet
3.6 The DDR Controller and the DDR Memory Devices
In general, setting the cpu_limit too low will block the CPU too frequently causing a
too high latency (execution time). Setting the cpu_limit too high can completely block
the soft real time DMA for a long time when the hard real time DMA and CPU
bandwidth are peaking. But perhaps the long latency that causes the soft real time
may not be a problem.
The DDR SDRAM Controller is compatible with most of the DDR SDRAM vendors.
This is achieved when the correct timing parameters are programmed in the MMIO
registers holdings the timing parameters has presented in the two following sections.
This section shows how programmable timing parameters direct the operation of the
DDR SDRAM Controller. It is not the intention of this section to give a complete
overview of all DDR interface signaling. Only the main ones are described.
timing diagrams.
Table 6: DDR Timing Parameters
Throughout all timing diagrams a DDR burst size of eight data elements is used.
In the timing diagrams, symbols are used to indicate the DDR commands that are
issued by the DDR controller. An overview of these commands and their symbol
convention are shown in
Table 7: DDR Commands
Parameter
CAS latency
Minimum time between two active commands to different banks
Minimum time between two active commands to same bank
Minimum time between auto refresh and active command
Minimum time after last data write and precharge to same bank
Minimum time between active and precharge command
Minimum time between precharge and active command
Minimum time between active and read command
Minimum time between active and write command
DDR Commands
Any DDR command
Activate command
Precharge command
Read command
Write command
Auto refresh command
Table 6
presents the values that are used for the different timing parameters in the
Rev. 2 — 1 December 2004
Table
7.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
Symbol
t
t
t
t
t
t
t
t
t
CAS
RRD
RC
RFC
WR
RAS
RP
RCD_RD
RCD_WR
Symbol
Any
Act
Pre
Read
Write
A. rf.
Value (Clock
Cycles)
2.5
3
8
8
1
8
4
4
2
9-20