PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 183

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
12NC 9397 750 14321
Product data sheet
Bit
6
5:3
2:1
0
Offset 0x04,7114
3
2:1
0
Offset 0x04,7118
31:6
5
4:3
31:4
Symbol
turn_off_ack
sel_clk_mbs_src
sel_clk_mbs
en_clk_mbs
Reserved
turn_off_ack
sel_clk_tstamp
en_clk_tstamp
Reserved
turn_off_ack
sel_lan_clk_src
CLK_TSTAMP_CTL
CLK_LAN_CTL
Acces
s
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
…Continued
Value
0
111
00
1
-
0
00
1
-
0
00
Rev. 2 — 1 December 2004
Description
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
000: clk_mbs_src = clk_144
001: clk_mbs_src = clk_123
010: clk_mbs_src = clk_108
011: clk_mbs_src = clk_96
100: clk_mbs_src = clk_86
101: clk_mbs_src = clk_78
110: clk_mbs_src = clk_72
111: clk_mbs_src = clk_66
00: clk_mbs = 27 MHz xtal_clk
01: clk_mbs = clk_mbs_src
10: clk_mbs = 27 MHz xtal_clk
11: clk_mbs = AI_SD[3]
1: enable clk_mbs
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_tstamp = 27 MHz xtal_clk
01: clk_tstamp = Source clock (clk_108)
10: clk_tstamp = Second Clock (clk_13_5)
11: clk_tstamp = AO_WS
1: enable clk_tstamp
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_lan_src = UNDEF
01: clk_lan_src = PLL1
10: clk_lan_src = DDS4
11: clk_lan_src = DDS7
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 5: The Clock Module
PNX15xx Series
5-39